Deep Learning-Based Cache Configuration Prediction for Field Programmable Gate Array-Accelerated Smart Vehicles

Cheshfar, Mohamad; MAGHAMI, MOHAMMAD HOSSEIN; GHARAEE GARAKANI,, HOSSEIN; AMIRI, PARVIZ

Volume 16, Issue 3 (9-2026) ASE 2026, 16(3): 5161-5177 | Back to browse issues page

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Cheshfar M, MAGHAMI M H, GHARAEE GARAKANI, H, AMIRI P. Deep Learning-Based Cache Configuration Prediction for Field Programmable Gate Array-Accelerated Smart Vehicles. , ASE. 2026; 16 (3) :5161-5177
URL: http://ase.iust.ac.ir/article-1-733-en.html

Deep Learning-Based Cache Configuration Prediction for Field Programmable Gate Array-Accelerated Smart Vehicles

Mohamad Cheshfar

, MOHAMMAD HOSSEIN MAGHAMI ^*

, HOSSEIN GHARAEE GARAKANI,

, PARVIZ AMIRI

Shahid Rajaee Teacher Training University

Abstract: (86 Views)

This paper presents a machine-learning framework for cache-configuration prediction in embedded Field Programmable Gate Array (FPGA) systems, with a particular focus on smart-vehicle and resource-constrained computing applications. The proposed method formulates cache tuning as a regression problem and predicts the number of sets, associativity, and block size from memory-access traces together with FPGA resource budgets. Unlike classification-based approaches limited to predefined cache classes, the proposed CNN–LSTM model supports continuous cache-space exploration and produces hardware-feasible configurations after discretization. Experimental results on MachSuite, PolyBench, and CHStone benchmarks demonstrate effective generalization to unseen workloads, achieving a validation MAE of 0.085 and a test-set miss-rate MAE of 0.064. On a Xilinx Zynq-7020 target, the predicted configurations reduced average CLB utilization from 19.13% to 15.38% of available resources, increased BRAM utilization from 59.86% to 70.00%, and lowered estimated on-chip power from 0.201 W to 0.196 W under XPE-based pre-implementation analysis. These results indicate that the proposed approach can significantly reduce the cost of exhaustive design-space exploration while preserving cache performance and hardware efficiency, making it a promising solution for embedded FPGA platforms used in smart-vehicle systems.

Keywords: Smart Vehicles, Cache Design, FPGA, Deep Learning

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Type of Study: Research | Subject: Autonomous vehicles