<?xml version="1.0" encoding="utf-8"?>
<journal>
<title>Automotive Science and Engineering</title>
<title_fa>Automotive Science and Engineering</title_fa>
<short_title>ASE</short_title>
<subject>Engineering &amp; Technology</subject>
<web_url>http://ase.iust.ac.ir</web_url>
<journal_hbi_system_id>18</journal_hbi_system_id>
<journal_hbi_system_user>agent2</journal_hbi_system_user>
<journal_id_issn>2717-2023</journal_id_issn>
<journal_id_issn_online>2717-2023</journal_id_issn_online>
<journal_id_pii></journal_id_pii>
<journal_id_doi>10.22068/ase</journal_id_doi>
<journal_id_iranmedex></journal_id_iranmedex>
<journal_id_magiran></journal_id_magiran>
<journal_id_sid></journal_id_sid>
<journal_id_nlai></journal_id_nlai>
<journal_id_science></journal_id_science>
<language>en</language>
<pubdate>
	<type>jalali</type>
	<year>1405</year>
	<month>6</month>
	<day>1</day>
</pubdate>
<pubdate>
	<type>gregorian</type>
	<year>2026</year>
	<month>9</month>
	<day>1</day>
</pubdate>
<volume>16</volume>
<number>3</number>
<publish_type>online</publish_type>
<publish_edition>1</publish_edition>
<article_type>fulltext</article_type>
<articleset>
	<article>


	<language>en</language>
	<article_id_doi></article_id_doi>
	<title_fa></title_fa>
	<title>Deep Learning-Based Cache Configuration Prediction for Field Programmable Gate Array-Accelerated Smart Vehicles</title>
	<subject_fa>خودروهای خودران</subject_fa>
	<subject>Autonomous vehicles</subject>
	<content_type_fa>پژوهشي</content_type_fa>
	<content_type>Research</content_type>
	<abstract_fa></abstract_fa>
	<abstract>&lt;span style=&quot;font-size:11.0pt&quot;&gt;&lt;span style=&quot;line-height:115%&quot;&gt;&lt;span calibri=&quot;&quot; style=&quot;font-family:&quot;&gt;&lt;span style=&quot;color:#222222&quot;&gt;This paper presents a machine-learning framework for cache-configuration prediction in embedded Field Programmable Gate Array (FPGA) systems, with a particular focus on smart-vehicle and resource-constrained computing applications. The proposed method formulates cache tuning as a regression problem and predicts the number of sets, associativity, and block size from memory-access traces together with FPGA resource budgets. Unlike classification-based approaches limited to predefined cache classes, the proposed CNN&amp;ndash;LSTM model supports continuous cache-space exploration and produces hardware-feasible configurations after discretization. Experimental results on MachSuite, PolyBench, and CHStone benchmarks demonstrate effective generalization to unseen workloads, achieving a validation MAE of 0.085 and a test-set miss-rate MAE of 0.064. On a Xilinx Zynq-7020 target, the predicted configurations reduced average CLB utilization from 19.13% to 15.38% of available resources, increased BRAM utilization from 59.86% to 70.00%, and lowered estimated on-chip power from 0.201 W to 0.196 W under XPE-based pre-implementation analysis. These results indicate that the proposed approach can significantly reduce the cost of exhaustive design-space exploration while preserving cache performance and hardware efficiency, making it a promising solution for embedded FPGA platforms used in smart-vehicle systems.&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;</abstract>
	<keyword_fa></keyword_fa>
	<keyword>Smart Vehicles , Cache Design,  FPGA ,Deep Learning</keyword>
	<start_page>5161</start_page>
	<end_page>5177</end_page>
	<web_url>http://ase.iust.ac.ir/browse.php?a_code=A-10-883-1&amp;slc_lang=en&amp;sid=1</web_url>


<author_list>
	<author>
	<first_name>Mohamad</first_name>
	<middle_name></middle_name>
	<last_name>Cheshfar</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>m.cheshfar@sru.ac.ir</email>
	<code></code>
	<orcid></orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Shahid Rajaee Teacher Training University</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>MOHAMMAD HOSSEIN</first_name>
	<middle_name></middle_name>
	<last_name>MAGHAMI</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>mhmaghami@sru.ac.ir</email>
	<code></code>
	<orcid></orcid>
	<coreauthor>Yes
</coreauthor>
	<affiliation>Shahid Rajaee Teacher Training University</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>HOSSEIN</first_name>
	<middle_name></middle_name>
	<last_name>GHARAEE GARAKANI,</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>hgharae@itrc.ac.ir</email>
	<code></code>
	<orcid></orcid>
	<coreauthor>No</coreauthor>
	<affiliation>ICT Research Institute</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>PARVIZ</first_name>
	<middle_name></middle_name>
	<last_name>AMIRI</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>pamiri@sru.ac.ir</email>
	<code></code>
	<orcid></orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Shahid Rajaee Teacher Training University</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


</author_list>


	</article>
</articleset>
</journal>
